The present invention relates generally to computer systems, and more specifically, to delaying execution in a processor in order to increase power savings potential.
In computer systems with multiple interconnected components (e.g., processors, accelerators, memory) it is often the case that some components are busy while others are idle. A standard method of reducing power usage by components during inactive intervals is to use power gating to activate sleep or power down modes. According to this method, the logic is built of low-threshold transistors, with high-threshold transistors serving as a footer or header to cut leakage during the quiescence intervals. During normal operation mode, the circuits achieve high performance, resulting from the use of low-threshold transistors. During sleep mode, high threshold footer or header transistors are used to cut off leakage paths, reducing the leakage currents by orders of magnitude. Another method of reducing the active power is transparent clock gating (TCG). TCG takes advantage of bubbles in a pipeline to avoid clocking latches when a pair of data items are separated by more than one clock cycle (i.e. not back-to-back), potentially reducing clock power by fifty percent in some units for normal workloads.
A general drawback associated with such techniques of power savings is that periods of idleness (or pipeline bubbles) for a given resource are often not long enough to support the overhead associated with activating and deactivating the power savings technique, even when the fraction of idle cycles relative to the total number of execution cycles is rather large.